1. Field of the Invention
The present invention relates to a VISS signal detecting method enabling detection of a VISS signal of a video tape by software in a microcomputer which can not use VISS detecting function of hardware, and a storage medium storing a computer program detecting the VISS signal.
2. Description of the Related Art
A VISS signal is a signal generated by writing a given amount (number within a standard) of VISS pulses, and is used for finding a video recording start position. In general, in a versing-up operation called as an index search or so forth, a video tape traveling at high speed is scanned to perform normal reproduction from a detecting position of the VISS signal. A VISS system is a system detects a VISS pulse generated by varying a falling edge timing of a phase position detecting signal recorded upon VTR recording and make a judge that the VISS signal is found when twenty-five or more VISS pulses are sequentially detected (under standard, skipping of the pulse in the extent of one pulse in sequential detection of the VISS pulses is permitted, judgment is made that the VISS signal is detected when twenty-five pulses is detected in detection of more than or equal to 90% of write pulses).
Discussion will be given about occurrence of delay at an interruption process start timing with reference to a timing chart of FIG. 9. At a timing 901 of FIG. 9, execution of a process A is initiated. When execution demand of a process B having higher preference than the process A and a process C having lower preference than the process A occur during execution of the process A, the process A on execution is interrupted, the process B is initiated and the process C is placed in waiting for process initiation.
When the process B is completed, execution of the process A having higher preference than the process C is resumed. The process C is thus executed after completion of the process A. In this condition, assuming that execution demand for an interrupt process D having preference lower than the process A but higher than the process C occurs at a timing 903, execution of the interrupt process D is initiated immediately after completion of the process A. Thus, execution of the process C is withheld until completion of the interrupt process D. In this case, a period 910 from occurrence of the execution demand for the process C to actual initiation of execution is referred to as interruption delay period.
In a VTR system, disturbance of drive control of a motor should results in distortion of the image. Accordingly, it is ideal to set preference of an interrupt process of motor drive control as high as possible. On the other hand, in order to minimize the interruption delay period in the motor drive control process, interrupt processes having higher priority than the motor drive control process are required to shorten the process periods as short as possible.
FIG. 10 is a timing chart showing the conventional VISS signal detecting operation, and FIG. 11 is a block diagram showing an example of a register construction within a microcomputer used for conventional VISS pulse and FIG. 12 is an illustration showing a VISS pulse standard.
Operation of VISS detection using the conventional hardware will be discussed with reference to FIGS. 10 to 12. In FIG. 11, a timer 1103 measures a period of one cycle of a phase position detection signal and is cleared by interruption of the phase position detection signal. On the other hand, a count value of the timer 1103 is stored in a comparing register 1102.
At first, on the basis of a period of the phase position detection signal before a measurement timing 1005 for measuring a period of the phase position detection signal, a VISS signal judgment timing during a period of the phase position detection signal after the measurement timing is derived. Here, the VISS signal judgment timing is a timing elapsed one half (50%) of the phase position detection signal period 1001 from the measurement timing 1005. Namely, on the basis of a level of the phase position detection signal at this timing, judgement is made whether the signal is the VISS signal. Namely, at a timing where a count value derived at the immediately preceding phase position detection signal period and stored in the comparing register 1102 and the count value of the timer 1103 are match, the level of the signal waveform of the phase position detection signal is confirmed. When the phase position detection signal level is Hi level, judgment is made that the VISS signal is found. If the phase detection signal level is Low level, judgement is made that the signal is normal pulse. On the other hand, the level of the phase position detection signal at this time is detected by a level detecting portion to store in a VISS detection buffer 1108. The VISS detection buffer 1108 shores data with shifting to the VISS signal judgment buffer 1108. When the value resulting by newly taking matches with a value of a signal judgement buffer 1109, namely the value already set as a pattern upon detection of VISS (in the shown example, when Hi level is detected continuously or sequentially for a times more than or equal to twenty-five times), finding of the VISS signal is judged to generate vector interrupt.
A series of operation set forth above is performed automatically by hardware (only performing setting of pattern of the VISS signal by software), by vector interrupt occurring only upon fining of a VISS mark, the process after fining of VISS is performed by the operation of the hardware.
Setting of the hardware for detection of the VISS signal in the operation set forth above, the VISS signal is detected using rising edge of the phase position detection signal by the detecting edge selector 101 of FIG. 11. By this, when rising edge of the phase position detection signal is detected, the count value of the timer corresponding to one cycle of the phase position detection signal is stored in the register 1102. Subsequently, the timer 1103 is cleared. A period corresponding to 50% of the count value stored in the register 1102 is stored in the register 1104. In the example of FIG. 10, at a timing 1005. a length of the period 1001 is the value of the timer 1103 stored in the comparing register 1102.
Then, after clearing the timer 1103, counting in the timer is progressed again. When the count value of the timer 1103 matches with the value of the register 1104 (namely, a period of 50% of the period 1101), the phase position detection signal is detected. Then, the level of the phase position detection signal at that time in the level detecting portion 1107 is buffered in the VISS detection buffer 1108 and compared with the value of the preliminarily set VISS signal judgment buffer 1109.
Repeating the foregoing process, when a result of the level being buffered in the VISS detection buffer 1108 and the value of the VISS signal judgment buffer 1109 match, the interrupt demand 1110 notifying detection of VISS signal is output. The interrupt demand 1110 is detected by the software.
In the prior art set forth above, the VISS signal detection process and the process up to detection of the VISS signal are performed automatically by the hardware. Therefore, delay of the detection position due to other interruption may not be caused. Therefore, detection of the phase position detection signal is possible, and thus, when the phase position detection signal detected can be used in detection of the VISS signal, such detection is effective. However, detection set forth above cannot be used in certain case for the problem discussed below.
At first, it is possible that there is another timer unit using the phase position detection signal as the detection edge (for example, register 1105 of FIG. 11) and in the process by the unit, setting for detecting both edges of rising and falling in the phase position detection signal in detection of the phase position detection signal of FIG. 10. Interrupt process of the register 1105 is performed by the process controlled by the phase control signal. However, due to large process load, division of the process content by detecting both edges of the phase position detection signal is performed. Thew capture operation edge of the register 1105, clearing of the timer 1103 and the capture operation edge of the register 1102 are generated at a timing of the same signal. Therefore, it is not possibly to set the edges to be used independently of the other.
Secondly, There is a case where intervals of the phase position detection signals is not constant in the condition performing VISS detection. Upon fast feeding (FF) and rewinding (REW), detection process of the VISS signal by operation of the incorporated hardware is performed by deriving the capture position for detecting the VISS signal on the basis of a period for one cycle of the phase position detection signal immediately before. Therefore, when speed of fast feeding or rewinding is increased sequentially without increasing in stepwise at every given period, if the speed variation amount is greater than or equal to 50%, the capture position may be set with a delay to possibly cause erroneous judgment.
Next, by software, discussion will be given for the conventional method for detecting the VISS by setting, in which both of rising and falling edges of the phase position detection signal are detected, with reference to FIGS. 12 to 14.
The shown example has a setting for performing clear of the timer by both edges of the phase position detection signal of FIG. 13. Therefore, in the register storing the count value of the timer (see register 1102 of FIG. 11), a value of a zone 1301 is stored at a timing 1302, a value of a zone 1303 is stored at a timing 1304 and a value of a zone 1305 is stored at a timing 1307. On the other hand, the value of the register is held until the occurrence of the next edge. Thus, it becomes possible to make reference to the value of the register during VISS pulse judgment process (FIG. 14) triggered by the edge.
The VISS pulse judgment process of FIG. 14 will be discussed hereinafter. The VISS pulse judgment process is triggered in response to each edge of the phase: position detection signal of FIG. 13. At first, as triggered by the edge of the phase position detection signal of the timing 1302 of FIG. 13, since the value of the edge counter is xe2x80x9c0xe2x80x9d in the initial state, the value of the register is stored in an xcex1 buffer (steps 1401 and 1402). Then, for updating the process content, the edge counter is updated to xe2x80x9c1xe2x80x9d (step 1403).
The foregoing edge counter is a counter for distributing the count value of the timer measuring the interval between the edges of the phase position detection signal and counts up at rising and falling edges of the phase position detection signal to sequentially count as first value, second value . . . as xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, . . . After counting up to the predetermined value, counting is resumed from the initial value. On the basis of the count value of the edge counter, the buffer to store the value of the register is determined.
Next, as triggered by the edge of the phase position detection signal at the timing 1304 of FIG. 13, the value of the edge counter is xe2x80x9c1xe2x80x9d. Therefore, the value of the register is stored in xcex2 buffer (steps 1401 and 1404. Then, by comparing the value stored in the xcex1 buffer and the value stored in the xcex2 buffer, judgment can be made whether the phase position detection signal is the VISS pulse or not (step 1405). If the phase position detection signal is VISS pulse, the value of the VISS pulse counter counting number of the VISS pulses is updated (step 1406), and otherwise, the count value of the VISS pulse counter is reset (step 1407). Then, in order to set the xcex1 buffer for storing next time, the edge counter is updated to xe2x80x9c0xe2x80x9d (step 1408).
Next, when judgment is made that the count value of the VISS pulse reaches the predetermined reference value, information indicative of detection of the VISS signal is generated (steps 1409 and 1410). It should be noted that it is possible to take a method to make judgement whether the VISS signal is detected or bot when the value of the VISS pulse counter reaches a given reference value by a VISS pulse count monitoring process executed at every predetermined period instead of making judgement whether the VISS signal is detected or not at every edge of the phase position detection signal.
However, since control of feeding amount of the tape has to be performed during detection of the VISS pulse, delay in initiation of VISS interrupt can be caused by interrupt control (such as tape speed control, tape phase control, rotary head speed control, rotary head phase control) having higher preference than VISS signal detection process. In the VISS signal detection process in the case where the tape is fed at a normal speed such as that upon reproduction, even if waiting of initiation of the VISS signal detection process can be caused by the interrupt process having higher preference, since sufficient period is present between respective edges (about 9.15 ms) as shown in FIG. 12A, skipping of the edge data will never be caused. However, when the tape is fed at high speed, such as those in fast feeding or rewinding, a period between the edges becomes small as shown in FIG. 12B (about 0.8 ms), if waiting of initiation of the VISS signal detection process is caused by interrupt process having higher preference, the next edge of the phase position detection signal can occur while the VISS signal detection process is in waiting state. Considering example of FIG. 13, interrupt of the VISS signal detection process occurs at a timing 1304, interrupt process 1305 having higher preference is executed. Therefore, initiation of the VISS signal detection process is delayed up to the timing 1306. As a result, the value of the register at the timing 1304 cannot be stored in the xcex2 buffer. On the other hand, since the edge occurring at a timing 1307 during process during interrupt process 1305 cannot be detected, the value of the register is overwritten upon initiation 1306 of the VISS signal detection process. Thus, the value of the register at the timing 1304 is erased.
Namely, setting of the process initiated at the timing 1306 is the process which has to be initiated at the timing 1304. Therefore, the value of the register is written in the xcex2 buffer. At this time, the value of the register has already been overwritten, the value of the register in the zone 1305 is written in the xcex2 buffer (the value of the register at the timing 130). Thus, normal judgement cannot be made.
On the other hand, in the conventional VISS signal detecting method discussed with reference to FIGS. 13 and 14, detection of the VISS signal cannot be performed upon high speed fast feeding or rewinding over five times of the tape feed speed.
As set forth above, as the prior art in detecting the VISS signal recorded in the video tape, the technology detecting the VISS signal by means of hardware, cannot be implemented by the microcomputer having not hardware construction. Even the microcomputer having hardware construction, it cannot be used for VISS signal detection.
On the other hand, the conventional method detecting the VISS signal by software encounters a problem that skipping in detection of the edge of the phase position detection signal can be caused at high speed feeding of the video tape to make it difficult to accurately detect the VISS signal.
An object of the present invention is to provide a VISS signal detection method by software which can detect an edge of phase position detection signal without skipping even at high speed feeding of a video tape, and a storage medium storing a computer program for detecting the VISS signal.
According to one aspect of the invention, a VISS signal detection method for performing detection of a VISS signal of a video tape comprises
a step of executing a taking-up process of an interval between edges per level edge of the VISS signal,
a step of performing a detection process of a VISS pulse, and
step of performing a detection process of the VISS signal on the basis of result of detection at the VISS pulse detection step,
the process of the edge interval taking-in step being set as an interrupt process having highest preference,
in the VISS pulse detection step,
by making reference to a count value of an edge counter for distributing count values of a timer measuring the edge interval of a phase position detection signal added to the VISS signal used in the edge interval taking-in step, presence and absence of delay in the process of the VISS pulse detected based on number of occurrence of the edge interval taking-in step occurring up to the VISS pulse detection step, and
when delay is caused, post process being performed for accurately performing detection process of the VISS depending upon delay and the edge interval taking-in process in the next cycle.
By this, even the frame immediately after occurrence of delay, the VISS pulse can be detected so as to enable detection of the VISS signal even at high speed feeding of the tape, such as upon fast feeding or rewinding.
In the preferred construction, the edge interval taking-in step comprises
step of checking a value of the edge counter,
step of storing a value of the register storing the count value of the timer in a first buffer when the value of the edge counter when the value of the edge counter is a predetermined first value,
step of storing a value of the register in a second buffer when the value of the edge counter when the value of the edge counter is a predetermined second value,
step of storing a value of the register in a third buffer when the value of the edge counter when the value of the edge counter is a predetermined third value, and
step of varying buffer for writing in a next value by updating the value of the edge counter in the case where the value of the edge counter is not any of the first value, second value and third value and after storing the value of the register in any one of the first buffer, second buffer and third buffer, and
the step of checking the value of the VISS counter comprises
operation being terminated without any process when the value of the edge counter is the second value, and in conjunction therewith,
step of making judgment whether the phase position detection signal is the VISS pulse by comparing the value of the register stored in the first buffer and the value of the register stored in the second buffer, updating the count value of the VISS counter when the phase position detection signal is judged as the VISS pulse and initializing the count value of the VISS pulse counter when the phase position detection signal is not judged as the VISS pulse, when the value of the edge counter is the third value,
step of making judgment whether the phase position detection signal is the VISS pulse by comparing the value of the register stored in the first buffer and the value of the register stored in the second buffer, updating the count value of the VISS counter when the phase position detection signal is judged as the VISS pulse, initializing the count value of the VISS pulse counter when the phase position detection signal is not judged as the VISS pulse and shifting the content of the third buffer to the first buffer by correcting a buffer information, when the value of the edge counter is the fourth value,
step of initializing a value of the VISS pulse counter when the value of the edge counter is not any the second value, third value and the four value, and
a step of initializing the edge counter after processing initialization of the counter value of the VISS counter after updating or initialization of the count value of the VISS pulse counter in the process when the value of the edge counter is the third value and when the value of the edge counter is not any of the second value, third value and fourth value.
In another preferred construction, the edge interval taking-in step further comprises step of notifying occurrence of a buffer error when the value of the edge counter becomes a predetermined fifth value by updating.
In another preferred construction, the edge interval taking-in step comprises
step of checking a value of the edge counter,
step of storing the value of the register storing a count value of a timer in a first buffer, when a VISS judgment reference period is set, comparing the VISS judgment reference value and a value of the first buffer to make judgement whether the phase position detection signal is the VISS pulse, when judgement is made that the phase position detection signal is the VISS pulse, updating the count value of the VISS pulse counter, and when judgement is not made that that the phase position detection signal is the VISS pulse, initializing the counter value of the VISS pulse counter, when the value of the edge counter is in a predetermined first value,
when the value of the edge counter when the value of the edge counter is a predetermined second value,
step of storing a value of the register in a third buffer when the value of the edge counter when the value of the edge counter is a predetermined third value, and
step of varying buffer to writing in the next value by updating the edge counter when the value of the edge counter is no any of a first value, second value and third value, after updating or initialization of the count value of the VISS pulse counter in the process when the value of the edge counter is the first value, storing the value of the register to any one of the second buffer and the third buffer, updating the edge counter for varying the buffer to writer in the next value,
the step of checking the value of the VISS counter comprises
operation being terminated without any process when the value of the edge counter is the second value, and in conjunction therewith,
step of terminating operation without performing any process when the value of the edge counter is a second value,
step of setting the VISS pulse judgment reference value by measuring a period of the phase position detection signal when the value of the edge counter is third value,
step of measuring a period of the phase position detection signal, setting the VISS pulse judgment reference period, shifting the content of the third buffer to the first buffer by correcting a buffer information, comparing set VISS pulse judgment reference period and the value of the first buffer, making judgment whether the phase position detection signal is the VISS pulse, updating the count value of the VISS pulse counter when the phase position detection signal is judged as VISS pulse and initializing the count value of the VISS pulse counter when the phase position detection signal is not judged as VISS pulse, when the value of the edge counter is a fourth value,
step of initializing the value of the VISS pulse counter when the value of the edge counter is not any of second value, third value and fourth value, and
step of initializing the edge counter after setting the VISS pulse judgement reference value and after a process of initializing the count value of the VISS counter when the value of the edge counter is not any of second value, third value and fourth value.
In another preferred construction, the edge interval taking-in step comprises
step of checking a value of the edge counter,
step of storing the value of the register storing a count value of a timer in a first buffer, when a VISS judgment reference period is set, comparing the VISS judgment reference value and a value of the first buffer to make judgement whether the phase position detection signal is the VISS pulse, when judgement is made that the phase position detection signal is the VISS pulse, updating the count value of the VISS pulse counter, and when judgement is not made that that the phase position detection signal is the VISS pulse, initializing the counter value of the VISS pulse counter, when the value of the edge counter is in a predetermined first value,
when the value of the edge counter when the value of the edge counter is a predetermined second value,
step of storing a value of the register in a third buffer when the value of the edge counter when the value of the edge counter is a predetermined third value, and
step of varying buffer to writing in the next value by updating the edge counter when the value of the edge counter is no any of a first value, second value and third value, after updating or initialization of the count value of the VISS pulse counter in the process when the value of the edge counter is the first value, storing the value of the register to any one of the second buffer and the third buffer, updating the edge counter for varying the buffer to writer in the next value,
the step of checking the value of the VISS counter comprises
operation being terminated without any process when the value of the edge counter is the second value, and in conjunction therewith,
step of terminating operation without performing any process when the value of the edge counter is a second value,
step of setting the VISS pulse judgment reference value by measuring a period of the phase position detection signal when the value of the edge counter is third value,
step of measuring a period of the phase position detection signal, setting the VISS pulse judgment reference period, shifting the content of the third buffer to the first buffer by correcting a buffer information, comparing set VISS pulse judgment reference period and the value of the first buffer, making judgment whether the phase position detection signal is the VISS pulse, updating the count value of the VISS pulse counter when the phase position detection signal is judged as VISS pulse and initializing the count value of the VISS pulse counter when the phase position detection signal is not judged as VISS pulse, when the value of the edge counter is a fourth value,
step of initializing the value of the VISS pulse counter when the value of the edge counter is not any of second value, third value and fourth value, and
step of initializing the edge counter after setting the VISS pulse judgement reference value and after a process of initializing the count value of the VISS counter when the value of the edge counter is not any of second value, third value and fourth value,
in the VISS detection step, a period half of a period the measured phase position detection signal is set as the VISS pulse judgment reference period.
Also, the edge interval taking-in step comprises
step of checking a value of the edge counter,
step of storing the value of the register storing a count value of a timer in a first buffer, when a VISS judgment reference period is set, comparing the VISS judgment reference value and a value of the first buffer to make judgement whether the phase position detection signal is the VISS pulse, when judgement is made that the phase position detection signal is the VISS pulse, updating the count value of the VISS pulse counter, and when judgement is not made that that the phase position detection signal is the VISS pulse, initializing the counter value of the VISS pulse counter, when the value of the edge counter is in a predetermined first value,
when the value of the edge counter when the value of the edge counter is a predetermined second value,
step of storing a value of the register in a third buffer when the value of the edge counter when the value of the edge counter is a predetermined third value, and
step of varying buffer to writing in the next value by updating the edge counter when the value of the edge counter is no any of a first value, second value and third value, after updating or initialization of the count value of the VISS pulse counter in the process when the value of the edge counter is the first value, storing the value of the register to any one of the second buffer and the third buffer, updating the edge counter for varying the buffer to writer in the next value,
the step of checking the value of the VISS counter comprises
operation being terminated without any process when the value of the edge counter is the second value, and in conjunction therewith,
step of terminating operation without performing any process when the value of the edge counter is a second value,
step of setting the VISS pulse judgment reference value by measuring a period of the phase position detection signal when the value of the edge counter is third value,
step of measuring a period of the phase position detection signal, setting the VISS pulse judgment reference period, shifting the content of the third buffer to the first buffer by correcting a buffer information, comparing set VISS pulse judgment reference period and the value of the first buffer, making judgment whether the phase position detection signal is the VISS pulse, updating the count value of the VISS pulse counter when the phase position detection signal is judged as VISS pulse and initializing the count value of the VISS pulse counter when the phase position detection signal is not judged as VISS pulse, when the value of the edge counter is a fourth value,
step of initializing the value of the VISS pulse counter when the value of the edge counter is not any of second value, third value and fourth value, and
step of initializing the edge counter after setting the VISS pulse judgement reference value and after a process of initializing the count value of the VISS counter when the value of the edge counter is not any of second value, third value and fourth value,
in the VISS detection step, a period half of a period the measured phase position detection signal is set as the VISS pulse judgment reference period.
the edge interval taking-in step further comprises a step of notifying occurrence of buffering error when the value of the edge counter becomes fifth value by updating.
According to another aspect of the invention, a computer readable memory storing a computer program performing detection of a VISS signal of a video tape by controlling a computer, the computer program comprises
a step of executing a taking-up process of an interval between edges per level edge of the VISS signal,
a step of performing a detection process of a VISS pulse, and
step of performing a detection process of the VISS signal on the basis of result of detection at the VISS pulse detection step,
the process of the edge interval talking-in step being set as an interrupt process having highest preference,
in the VISS pulse detection step,
by making reference to a count value of an edge counter for distributing count values of a timer measuring the edge interval of a phase position detection signal added to the VISS signal used in the edge interval taking-in step, presence and absence of delay in the process of the VISS pulse detected based on number of occurrence of the edge interval taking-in step occurring up to the VISS pulse detection step, and
when delay is caused, post process being performed for accurately performing detection process of the VISS depending upon delay and the edge interval taking-in process in the next cycle.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.